Method 1: Using Only pma_rx_clk0 (Provided by the Example Design) - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English
Figure 1. Ten-Bit Interface Receiver Logic – Kintex 7 Devices (Example Design) pma_rx_clk0 BUFIO IOB LOGIC IP AD rx_code_g roup[0] IB UF IP AD pma_rx_clk0 B UFR IOB LOGIC pma_rx_clk1 rx_code_g roup0[0] rx_code_g roup1[0] IDDR Q1 D Q2 C IODEL A Y D Q D Q X12877 <component_name>_block EncryptedRTL

The device logic used by the example design delivered with the core is shown in the previous figure. This shows an IDDR primitive used with the DDR_CLK_EDGE attribute set to SAME_EDGE. This uses local inversion of pma_rx_clk0 within the IOB logic to receive the rx_code_group[9:0] data bus on both the rising and falling edges of pma_rx_clk0 . The SAME_EDGE attribute causes the IDDR to output both Q1 and Q2 data on the rising edge of pma_rx_clk0.

For this reason, pma_rx_clk0 can be routed to both pma_rx_clk0 and pma_rx_clk1 clock inputs of the core as shown.

This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180° out of phase with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data sheet for the attached SerDes to verify that this is the case.

Setup and hold is achieved using a combination of IODELAY elements on the data and using BUFIO and BUFR regional clock routing for the pma_rx_clk0 input clock, as shown in the previous figure.

In the previous figure's implementation, a BUFIO is used to provide the lowest form of clock routing delay from input clock to input rx_code_group[9:0] signal sampling at the device IOBs. However, this creates placement constraints; a BUFIO capable clock input pin must be selected for pma_rx_clk0, and all rx_code_group[9:0] input signals must be placed in the respective BUFIO region. See the FPGA user guides for more information.

The clock is then placed onto regional clock routing using the BUFR component and the input rx_code_group[9:0] data immediately resampled as shown.

The IODELAY elements can be adjusted to fine-tune the setup and hold times at the TBI IOB input flip-flops. The delay is applied to the IODELAY element using constraints in the XDC; these can be edited if required.