General Checks - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English
  • Ensure that all the timing constraints for the core were met during Place and Route.
  • Does it work in timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue.
  • Ensure that all clock sources are clean. If using DCMs in the design, ensure that all DCMs have obtained lock by monitoring the locked port.
  • If Clock Data Recovery (CDR) is not done on the board, increase RX_CDRLOCK_TIME parameter in the gtwizard_init file. This value is silicon-specific. The value given by default is a typical value and can be increased to the maximum TDLOCK value as specified in the device datasheet.
  • For BASE-X/SGMII modes in UltraScale devices, if the transceiver is not coming out of the reset sequence, check the following:
    1. If the Transceiver Control and status is enabled, check the DRP clock frequency. The frequency should be exactly same as that selected through DrpClkRate. It is recommended to connect the independent clock to the same clock frequency.
    2. If (a) is not applicable the independent clock frequency must be exactly same as that selected through the Vivado IDE GUI or through the parameter DrpClkRate. The DRP clock internally is connected to the independent clock in this case.