The following table lists the ports added from v15.0 of the core to v15.1.
In/Out | Port Name and Width | Description | What to do |
---|---|---|---|
Input | gt_gtrefclk1 | Reference clock option for AMD UltraScale+™ /AMD UltraScale™ GT. This is enabled only when debug ports are enabled. | |
Input | gt_cpllrefclksel[2:0] | Reference clock select line for UltraScale+/UltraScale GT. This is enabled only when debug ports are enabled. | Default value is 3'b001 for gtrefclk0 |
Input | refclk625_p | LVDS reference clock when LvdsRefclk is selected as 625 MHz. 1 | |
Input | refclk625_n | LVDS reference clock when LvdsRefclk is selected as 625 MHz. 1 | |
Input | refclk156_25_p | LVDS reference clock when LvdsRefclk is selected as 156.25 MHz. 1 | |
Input | refclk156_25_n | LVDS reference clock when LvdsRefclk is selected as 156.25 MHz. 1 | |
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