At SGMII, 100 Mbps, each byte is repeated 10 times. This also applies to the interframe gap period. For this reason, the minimum of 8 bytes for the 1 Gbps case corresponds to a minimum of 80 bytes for the 100 Mbps case.
Additionally, the majority of characters in this 80-byte interframe-gap period are going to be the /I2/ clock correction characters. Because of the clock correction circuitry design, a minimum of 20 /I2/ code groups will be available for removal. This translates into 40 bytes, giving a maximum run size of 40 x 5000 = 200000 bytes. Because each byte at 100 Mbps is repeated ten times, this corresponds to an Ethernet frame size of 20000 bytes, the same size as the 1 Gbps case.
So in summary, at 100 Mbps, for any frame size of 20000 bytes or less, it can still be assumed that the elastic buffer will return to half full occupancy before the start of the next frame. However, a frame size of 20000 is larger than can be received in the device-specific transceiver elastic buffer (see Receive Elastic Buffers: Depths and Maximum Frame Sizes). Only the SGMII FPGA Logic receive elastic buffer is large enough.