Transceiver Logic for 7 Series and Zynq 7000 Devices - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document ID
Release Date
16.2 English

The core is designed to integrate with 7 series and Zynq 7000 FPGA transceivers. The connections and logic required between the core and transceiver are shown in the following figure for Virtex 7. Kintex 7and Zynq 7000devices; the connections for Artix 7 devices are shown in uon1664789800031.html#uon1664789800031__image_t5b_knl_hvb.

The following figures show the connectivity of clocking logic with an encrypted core and transceiver channel. The internal signal names of the GT_CHANNEL or the encrypted RTL might not exactly correspond to the block level port names. For connectivity purposes at the block level see Port Descriptions. For shared logic connectivity guidelines see Clock Sharing Across Multiple Cores with Transceivers. The clock buffer on RXOUTCLK in the diagrams is a part of the clocking logic shown below for simplification.

The 125 MHz differential reference clock is routed directly to the transceiver. The transceiver is configured to output 62.5 MHz (125 MHz for 2.5G) clock on the txoutclk port; this is then routed to an MMCM through a BUFG (global clock routing. From the MMCM, the clkout0 port (125 MHz for 1G and 312.5 MHz for 2.5G) is placed onto global clock routing and can be used as the 125/312.5 MHz clock source for all core logic.

From the MMCM, the clkout1 port (62.5 MHz for 1G and 156.25 MHz for 2.5G) is placed onto global clock routing and is input back into the transceiver on the user interface clock port txusrclk and txusrclk2. The clocking logic is included in a separate module <component_name>_clocking which is instantiated in the <component_name>_support module.

It can be seen from the following figures that the receive elastic buffer is implemented in the FPGA logic between the transceiver and the core; this replaces the receive elastic buffer in the transceiver.

This alternative receive elastic buffer uses a single block RAM to create a buffer twice as large as the one present in the transceiver. It is able to cope with larger frame sizes before clock tolerances accumulate and result in emptying or filling of the buffer. This is necessary to guarantee SGMII operation at 10 Mbps where each frame size is effectively 100 times larger than the same frame would be at 1 Gbps because each byte is repeated 100 times (see Using the Client-Side GMII for the SGMII Standard).

With this FPGA logic receive elastic buffer implementation, data is clocked out of the transceiver synchronously to rxoutclk. This clock can be placed on a BUFMR followed by a BUFR (Virtex 7 only) or a BUFG (Kintex 7, Artix 7and Zynq 7000) and is used to synchronize the transfer of data between the transceiver and the elastic buffer, as shown in the following figures.

The two wrapper files around the GTX/GTH transceiver, gtwizard_gt and gtwizard are generated from the 7 series FPGA transceiver wizard. These files apply all the Gigabit Ethernet attributes. Consequently, these files can be regenerated by customers. See Regeneration of 7 Series/Zynq 7000 Transceiver Files for more information.

Figure 1. 1G SGMII Transceiver Connections (Virtex 7, Kintex 7, Zynq 7000)
Figure 2. 1G SGMII Transceiver Connections (Artix 7)