Problems in Obtaining a Link (Auto-Negotiation Disabled) - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2023-11-01
Version
16.2 English
Determine whether the device has successfully obtained a link with its link partner by doing the following:
  • Reading bit 1.2, Link Status, in MDIO Register 1: Status register , (see Register 1: Status Register) when using the optional MDIO management interface (or look at status_vector[1]).
  • Monitoring the state of status_vector[0] . If this is logic 1, then synchronization, and therefore a link, has been established. See bit 0 in Table 3.
If the devices have failed to form a link then do the following:
  • Ensure that auto-negotiation is disabled in both the core and in the link partner (the device or test equipment connected to the core).
  • Monitor the state of the signal_detect signal input to the core. This should either be:
    • Connected to an optical module to detect the presence of light. Logic 1 indicates that the optical module is correctly detecting light; logic 0 indicates a fault. Therefore, ensure that this is driven with the correct polarity.
    • Signal must be tied to logic 1 (if not connected to an optical module).
      Note: When signal_detect is set to logic 0, this forces the receiver synchronization state machine of the core to remain in the loss of sync state.
    • See Problems with a High Bit Error Rate in a subsequent section.
When using a device-specific transceiver, perform these additional checks:
  • Ensure that the polarities of the txn/txp and rxn/rxp lines are not reversed. If they are, this can be fixed by using the txpolarity and rxpolarity ports of the device-specific transceiver.
  • Check that the device-specific transceiver is not being held in reset by monitoring the mgt_tx_reset and mgt_rx_reset signals between the core and the device-specific transceiver. If these are asserted then this indicates that the PMA PLL circuitry in the device-specific transceiver has not obtained lock; check the PLL Lock signals output from the device-specific transceiver.
  • Monitor the RXBUFERR signal when auto-negotiation is disabled. If this is being asserted, the Elastic Buffer in the receiver path of the device-specific transceiver is either under or overflowing. This indicates a clock correction issue caused by differences between the transmitting and receiving ends. Check all clock management circuitry and clock frequencies applied to the core and to the device-specific transceiver.