1000BASE-X with TBI Example Design - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following figure shows the example design for a top level HDL with a 10-bit interface (TBI). The 2.5G mode is not supported in this case.

Figure 1. Example Design HDL for the Core with TBI