Transmitter Logic - 16.2 English

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

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16.2 English

The following figure shows the use of the physical transmitter interface of the core to create an external TBI. The signal names and logic shown exactly match those delivered with the example design when TBI is chosen. If other families are chosen, equivalent primitives and logic specific to that family are automatically used in the example design.

The following figure shows that the output transmitter datapath signals are registered in device IOBs before driving them to the device pads. The logic required to forward the transmitter clock is also shown. The logic uses an IOB output Double-Data-Rate (DDR) register so that the clock signal produced incurs exactly the same delay as the data and control signals. This clock signal, pma_tx_clk, is inverted with respect to gtx_clk so that the rising edge of pma_tx_clk occurs in the center of the data valid window to maximize setup and hold times across the interface.

Figure 1. Ten-Bit Interface Transmitter Logic