| 11/01/2023 Version
16.2 |
|
Transceiver Logic for Versal Devices
|
Added. |
|
Asynchronous 1000BASE-X/SGMII over LVDS
|
Updated. |
|
IP Facts
|
Updated. |
| 05/24/2023 Version
16.2 |
|
Asynchronous 1000BASE-X/SGMII over LVDS
|
Updated the section |
|
Synchronous SGMII over LVDS Using Component Mode
|
Updated the section. |
| 11/25/2022 Version
16.2 |
|
Asynchronous SGMII/1000BASE-X Over LVDS
|
Added a note. |
| 07/08/2022 Version
16.2 |
| N/A |
For Versal devices, the GEM support is added in the GUI. |
| 06/16/2021 Version
16.2 |
| N/A |
Async LVDS mode configuration is supported for Versal ACAP
devices. |
| 02/04/2021 Version
16.2 |
| N/A |
Added information for Versal. |
| 06/26/2020 Version
16.2 |
|
Configuration and Status Vector Ports
|
Updated an_restart_config signal description. |
|
Customizing and Generating the Core
|
Updated figures. |
|
Resets
|
Updated the section. |
| 05/22/2019 Version
16.1 |
|
Register 1: Status Register
|
|
| 11/14/2018 Version
16.1 |
| N/A |
- Added preamble shrinkage bullet in Features.
- Updated Device Specific Transceiver columns for Artix 7 in
Table 2.
|
| 10/04/2017 Version
16.1 |
| N/A |
Added 2500BASE-X support for Zynq 7000 devices in
Table 2. |
| 06/07/2017 Version
16.1 |
| N/A |
Added gtpowergood
output port for UltraScale and UltraScale+ device families. |
| 04/05/2017 Version
16.0 |
|
Upgrading
|
Updated tables in Appendix B (Migrating and Upgrading) for ports
and parameters for Asynchronous 1000BASE-X/SGMII over LVDS for UltraScale and UltraScale+ device
families |
| 10/05/2016 Version
16.0 |
| 16.0 |
- Added support for Asynchronous 1000BASE-X/SGMII over LVDS for
UltraScale and UltraScale+ device families.
- Added support to provide GT_Location in Vivado IDE.
- Added support for Spartan-7 devices.
- Added support for clock correction on /C1/,/C2/ code groups
in receive elastic buffer.
|
| 04/06/2016 Version
15.2 |
| N/A |
- Added support for GT in example design for UltraScale and
UltraScale+ devices.
- Added support for RX GMII interface to work at RXOUTCLK.
- Added support for Virtex UltraScale+ family.
- Added selection option for GTH and GTY transceivers for
UltraScale and UltraScale+ devices.
- Added support to interface with Gigabit Ethernet MAC of
Zynq
UltraScale+ devices.
|
| 11/18/2015 Version
15.1 |
| N/A |
Added support for UltraScale+ families. |
| 09/30/2015 Version
15.1 |
| N/A |
- Added 2.5G support for Artix devices (-2 and -3 speed
grades).
- Added LvdsRefClk for LVDS reference clock selection for
UltraScale devices.
- Added gt_gtrefclk1, gt_cpllrefclksel[2:0] in UltraScale debug signals.
- Updated Register 2 and Register 3 values.
|
| 04/01/2015 Version
15.0 |
| 15.0 |
- Added 2.5 Gbps support for 7 series devices (except Artix 7
and Zynq devices with Artix fabric) and UltraScale devices.
- Added options for gtrefclk and DRP/Free run clock selection
for UltraScale devices.
- Added txinhibit to the transceiver debug signals.
- Added pcsrsvdin to the transceiver debug signals for UltraScale devices.
- Added mmcm_reset port for modes using transceivers.
|
| 10/01/2014 Version
14.3 |
| N/A |
- Added 1588(PTP) GTH transceiver support for UltraScale architecture.
- Document re-structured.
- Added information on shared logic for cases using
device-specific transceiver.
|
| 04/02/2014 Version
14.2 |
| N/A |
- Added SGMII over LVDS for UltraScale devices.
- Modified status_vector(0) and LINK_STATUS register to take
care of reset sequence completion of transceivers.
- Updated screen displays in chapter 13.
- Added reset_done signal to several figures.
- Added External MDIO feature.
- Modified ambiguous text for BUFG usage in 7 series device
SGMII over LVDS.
|
| 12/18/2013 Version
14.1 |
| N/A |
- Added UltraScale architecture support.
- Added 1588(PTP) GTH transceiver support in the core.
- Updated screen displays in Chapter 13.
|
| 10/02/2013 Version
14.0 |
| N/A |
- Removed link timer value ports from block_wrapper
- Enhanced support for IP integrator.
- Reduced warnings in synthesis and simulation.
- Updated clock synchronizers to improve Mean Time Between
Failures (MTBF) for metastability.
- Added optional transceiver control and status ports.
- Added Vivado IDE option
to include or exclude shareable logic resources in the core.
- Added new board Vivado
IDE tab for targeting evaluation boards.
|
| 06/19/2013 Version
13.0 |
| N/A |
- Revision number advanced to 13.0 to align with core version
number 13.0.
- Added Zynq 7000 SoC EMAC support.
- Added 1588 (PTP) support in the core.
- Modified PHYAD to be a GUI option instead of block level
port.
- Updated Figures 2-2, 2-3, 2-6, 2-7, 2-8, 2-9, 13-1, 13-2,
13-3, and 13-4.
|
| 03/20/2013 Version
2.0 |
| N/A |
- Updated to core version 12.0.
- Removed all material related to devices not supported by the
Vivado Design Suite.
- Removed all material related to ISE® Design Suite, CORE
Generator™ tools,and UCF.
- Updated 7 series FPGA transceivers diagrams.
- Added Zynq support for SGMII over LVDS feature.
|
| 12/18/2012 Version
1.2 |
|
Debugging
|
- Updated for 14.4 and 2012.4. Updated to core version
11.5.
- Updated Debugging appendix.
- Added new information about Zynq 7000 FPGAs throughout the
guide
- Added XCI file information.
- Added statement about wait time for Vivado Design Suite use
with transceiver wizards.
- Updated Figures 6-8, 6-9, 6-10, 6-17, 7-2, and G-1.
- Added XDC information.
|
| 10/16/2012 Version
1.1 |
| N/A |
- Updated for 14.3 and 2012.3.
- Added Gigabit Ethernet EDK application for Zynq 7000
devices.
|
| 07/25/2012 Version
1.0 |
| N/A |
Initial Xilinx release in product guide format. This document
is based on the following documents:
- LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.3
Product Guide
- LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.3 Data
Sheet
|