| 05/30/2024 Version
2.6 |
|
Product Specification
|
Updated the following topics:
|
|
Designing with the Core
|
Updated DSA Operation Details (Gen 3/DFE),
VOP Update (Gen 3/DFE), and Quadrature Modulator Correction. |
|
Example Design
|
Removed Digital Data Block section. |
| 10/18/2023 Version 2.6 |
|
Designing with the Core
|
|
|
Zynq UltraScale+ RFSoC RF Data Converter Bare-metal/Linux Driver
|
Updated struct XRFdc
to clarify that a flag has been deprecated. Added a new
parameter in struct XRFdc_DACBlock_DigitalDataPath_Config and struct XRFdc_ADCBlock_DigitalDataPath_Config.
|
| 05/10/2023 Version
2.6 |
|
Product Specification
|
Updated Configuration Interface Ports,
AXI4-Stream Related Ports for RF-DACs, AXI4-Stream Related Ports for RF-ADCs
|
|
Clearing Threshold Flags
|
Updated section |
|
RF-DAC Multi-Band Operation
|
Clarified DAC data scalar description |
|
Multi-Tile Synchronization
|
Clarified the requirements for multi-tile
synchronization |
| 10/21/2022 Version
2.6 |
|
Tile <n> Registers
|
Clarified table note |
|
RF-ADC Digital Datapath
|
Added missing 10 in DDC |
|
Clearing Threshold Flags
|
Added additional information on clearing
flags |
|
Background Calibration Process
|
Updated timing constant setting
information |
|
Getting/Setting Calibration Coefficients
|
Added information about unfreezing calibration
|
|
RF-ADC Interface Data and Clock Rates
|
Removed redundant statement |
|
RF-DAC Interface Data and Clock Rates
|
Added IQMode after the formula |
|
Determining Gain-Change Latency
|
Added additional information about the
compensation method |
| 04/20/2022 Version
2.6 |
|
Real-Time DSA Signal Interface for Quad RF-ADCs (Gen 3/DFE)
|
Updated section |
|
Real-Time TDD Signals for Dual RF-ADCs (Gen 3/DFE)
|
Updated section |
|
Real-Time TDD Signal Interface for Quad RF-ADCs (Gen 3/DFE)
|
Updated section |
|
Real-Time TDD Signal Interface Ports for RF-DACs (Gen 3/DFE)
|
Updated section |
|
Compensation Using PL Gain
|
Updated section |
|
SYSREF Signal Requirements
|
Updated section |
|
References
|
Added new reference |
|
Detailed Description
|
Updated section |
|
Post-Implementation Simulation Speedup Register (0x0100)
|
Updated section |
|
DSA Operation Details (Gen 3/DFE)
|
Updated section |
|
RF-DAC Multi-Band Operation
|
Updated section |
|
RF-ADC Multi-Band Operation
|
Updated section |
|
TDD RX/Obs Sharing Mode
|
Updated section |
|
Getting/Setting Calibration Coefficients
|
Updated section |
|
Over Voltage (Gen 1/Gen 2)
|
Updated section |
| 10/27/2021 Version
2.6 |
|
Features
|
Updated number of tiles |
|
Dual and Quad RF-ADC/RF-DAC Tiles
|
Updated section |
|
External Clock Inputs
|
Updated section |
|
AXI4-Stream Related Ports for RF-DACs
|
Updated description for sXY_axis_tvalid |
|
Calibration Freeze Ports for Quad RF-ADC Tiles
|
adcXY_sig_detect added |
|
Calibration Freeze Ports for Dual RF-ADC Tiles
|
adcX_ZZ_sig_detect added |
|
Getting/Setting Calibration Coefficients
|
Updated section |
|
RF-DAC Analog Outputs
|
Updated section |
|
Consistent Common Mode Voltage (Gen 3/DFE)
|
Updated section |
|
RF-DAC IP Configuration
|
Updated timing diagrams |
|
PLL Reference Clock Forwarding (Gen 3/DFE)
|
Updated figure |
|
Sample Rate Clock Forwarding (Gen 3/DFE)
|
Updated figure |
|
Power-Down Tile
|
Power-Down Tile
|
|
Multi-Tile Synchronization
|
Multi-tile synchronization process updated for
powering down tiles in Gen 3 devices. Updated Detailed Description, Synchronization Steps,
and Deterministic Multi-Tile Synchronization API Use. |
|
Gating Analog SYSREF with Real-Time Signals (Gen 3/DFE)
|
Updated section |
|
Advanced Tab
|
Added Variable Fabric Width |
|
User Parameters
|
Added Variable Fabric Width parameters |
|
XRFdc_MultiConverter_Init
|
Updated RefTile description |
| 06/16/2021 Version
2.5 |
|
Dual and Quad RF-ADC/RF-DAC Tiles
|
Updated table |
|
External Clock Inputs
|
Added |
|
Real-Time Signal Interface Ports for RF-DACs
|
Added datapath_overflow signal |
|
Real-Time NCO Signal Interface Ports for RF-DACs
|
Updated tile reference |
|
Real-Time Signal Interface Ports for Quad RF-ADCs
|
Updated datapath_overflow signal |
|
Real-Time Signal Interface Ports for Dual RF-ADCs
|
Updated datapath_overflow signal |
|
Real-Time TDD Signal Interface for Quad RF-ADCs (Gen 3/DFE)
|
Updated |
|
Real-Time TDD Signals for Dual RF-ADCs (Gen 3/DFE)
|
Added note #2. |
|
AXI4-Stream Observation Channel Ports for RF-ADCs (Gen 3/DFE)
|
Updated |
|
RF-ADC Mixer with Numerical Controlled Oscillator
|
Updated fine mixer description |
|
Background Calibration Process
|
Added AutoCal mode |
|
Calibration Modes
|
Updated AutoCal description |
|
RF-ADC Multi-Band Operation
|
Updated section |
|
Transmit Transfer Function
|
Added Vcm description |
|
Consistent Common Mode Voltage (Gen 3/DFE)
|
Added |
|
Gain Calibration Block (GCB)
|
Updated description |
|
Time Skew Calibration Block (TSCB)
|
Updated description |
|
VOP Update (Gen 3/DFE)
|
Updated figures |
|
RF-DAC Numerical Controlled Oscillator and Mixer
|
Updated fine mixer description |
|
On-chip Clock Distribution (Gen 3/DFE)
|
Updated description |
|
PLL Reference Clock Forwarding (Gen 3/DFE)
|
Added |
|
Sample Rate Clock Forwarding (Gen 3/DFE)
|
Added |
|
RF-DAC Sample Rate Derating (Gen 3/DFE)
|
Added |
|
External T1 Clock Forwarding to RF-ADC (Gen 3/DFE)
|
Updated clock distribution |
|
On-chip PLL Clock Forwarding to RF-ADC (Gen 3/DFE)
|
Updated clock distribution |
|
Power-on Sequence Steps
|
Updated 11-13 sequence |
|
TDD Power Saving Mode
|
Added link |
|
Bitstream Reconfiguration
|
Updated description and #4 |
|
Synchronization Steps
|
Added digital settings description |
|
Analog SYSREF Capture/Receive
|
Updated tile description |
|
Multi-Tile Mode
|
Updated tile description |
|
Basic Tab
|
Updated section |
|
Converter Setup
|
Added description |
|
RF-ADC Tab
|
Updated Gen 3 figure |
|
RF-ADC Tile Configuration
|
Updated tile description |
|
RF-ADC Converter Configuration
|
Removed observation description |
|
Data Settings
|
Added observation channel description |
|
RF-DAC Tile Configuration
|
Updated tile description |
|
Advanced Tab
|
Updated section |
|
User Parameters
|
Added observation channel user
parameters |
|
Changes from V2.4 to V2.5
|
Added |
|
Overview
|
Added APIs |
|
XRFdc_MultiConverter_Init
|
Added RefTile |
|
XRFdc_Get_TileBaseAddr to XRFdc_GetMinSampleRate
|
Code cleanup |
|
XRFdc_CustomStartUp
|
Added |
|
XRFdc_SetDACDataScaler and XRFdc_GetDACDataScaler
|
Added |
|
XRFdc_IntrEnable
|
Updated |
| 11/30/2020 Version
2.4 |
|
Features
|
Updated section |
|
Overview
|
Added TDD and updated descriptions and figures |
|
Dual and Quad RF-ADC/RF-DAC Tiles
|
Updated section |
|
Tn Clock
|
Minor update |
|
API and Registers Access
|
Updated section |
|
AXI4-Stream Related Ports for RF-DACs
|
Updated sX_axis_aresetn description |
|
AXI4-Stream Related Ports for RF-ADCs
|
Updated sX_axis_aresetn description |
|
Real-Time TDD Signal Interface Ports for RF-DACs (Gen 3/DFE)
|
Added section |
|
Real-Time TDD Signals for Dual RF-ADCs (Gen 3/DFE)
|
Added Real-time TDD Signals for Dual ( Gen 3) |
|
AXI4-Stream Observation Channel Ports for RF-ADCs (Gen 3/DFE)
|
Added section |
|
Converter 0 Interrupt Register (0x0208)
|
Updated Bit[13] |
|
Converter 0 Interrupt Enable Register (0x020C)
|
Updated Bit[13] |
|
Converter 1 Interrupt Register (0x0210)
|
Updated Bit[13] |
|
Converter 1 Interrupt Enable Register (0x0214)
|
Updated Bit[13] |
|
Converter 2 Interrupt Register (0x0218)
|
Updated Bit[13] |
|
Converter 2 Interrupt Enable Register (0x021C)
|
Updated Bit[13] |
|
Converter 3 Interrupt Register (0x0220)
|
Updated Bit[13] |
|
Converter 3 Interrupt Enable Register (0x0224)
|
Updated Bit[13] |
|
DSA Operation Details (Gen 3/DFE)
|
Minor update |
|
Outside Common-Mode (Gen 3/DFE)
|
Minor update |
|
RF-ADC Decimation Filters (Gen 3/DFE)
|
Added bypass description |
|
Decimation Filter Details (Gen 3/DFE)
|
Updated code blocks |
|
Calibration Modes
|
Added |
|
Dual RF-ADC I/Q Input to I/Q Output
|
Added Important note |
|
VOP Details (Gen 3/DFE)
|
Updated VOP description |
|
VOP Update (Gen 3/DFE)
|
Updated section |
|
Inverse Sinc Filter for Mix-Mode (Gen 3/DFE)
|
Added N(bit) description |
|
RF-DAC Interpolation Filters (Gen 3/DFE)
|
Added 10x |
|
Interpolation Filter Details (Gen 3/DFE)
|
Added N(bit) description |
|
Image Rejection Filter Details (Gen 3/DFE)
|
Updated code block |
|
RF-DAC Datapath Mode (Gen 3/DFE)
|
Minor update |
|
RF-DAC Multi-Band Operation
|
Updated overflow description and Multi-Band Logic
figure |
|
Dual RF-DAC I/Q Input to Real Output (Gen 3/DFE)
|
Minor update |
|
Dual RF-DAC I/Q Input to I/Q Output (Gen 3/DFE)
|
Minor update |
|
Quad RF-DAC I/Q Input to Real Output
|
Minor update |
|
Dynamic Update Events
|
Added MTS description |
|
Interrupt Handling
|
Updated table |
|
On-chip Clock Distribution (Gen 3/DFE)
|
Updated section |
|
RF-ADC Analog Supply Power Sequencing (Gen 3/DFE)
|
Minor update |
|
TDD Mode (Gen 3/DFE)
|
Minor update |
|
TDD Power Saving Mode
|
Updated section |
|
TDD RX/Obs Sharing Mode
|
Updated section |
|
Multi-Tile Synchronization
|
Minor update |
|
Detailed Description
|
Added MTS description |
|
Synchronization Steps
|
Updated #5 and added note description |
|
Deterministic Multi-Tile Synchronization API Use
|
Updated MTS description |
|
SYSREF Signal Requirements
|
Updated MTS description |
|
PL SYSREF Capture
|
Updated MTS description |
|
Analog SYSREF Capture/Receive
|
Updated MTS description |
|
Analog SYSREF AC- and DC-Coupling
|
Minor update |
|
Main Sequence to Perform Synchronization for AC or DC Coupled Single or Multiple Device
|
Updated section |
|
Use Case 1: Synchronize Digital Features Using SYSREF for Single Device with AC- or DC-Coupling
|
Updated section |
|
Use Case 2: Synchronize Digital Features Using SYSREF for Multiple Devices with DC-Coupling
|
Updated section |
|
Gating Analog SYSREF with Real-Time Signals (Gen 3/DFE)
|
Added |
|
Single Converter Mode
|
Minor update |
|
Multi-Tile Mode
|
Minor update |
|
Basic Tab
|
Updated figures |
|
RF-ADC Tab
|
Updated figure |
|
RF-ADC Converter Configuration
|
Added TDD description |
|
Analog Settings
|
Added Autocal description |
|
RF-DAC Tab
|
Updated figure |
|
RF-DAC Converter Configuration
|
Minor update |
|
Data Settings
|
Minor update |
|
User Parameters
|
Added observation description |
|
RF-ADC Data Capture Block
|
Added note |
|
RF-DAC Data Stimulus Block
|
Added note |
|
XRFdc_ResetNCOPhase
|
Updated description |
|
XRFdc_SetDACVOP (Gen 3/DFE)
|
Updated description |
|
struct XRFdc_Pwr_Mode_Settings (Gen 3/DFE)
|
Added |
|
XRFdc_SetDecimationFactorObs (Gen 3/DFE)
|
Added |
|
XRFdc_GetDecimationFactorObs (Gen 3/DFE)
|
Added |
|
XRFdc_GetFabWrVldWordsObs (Gen 3/DFE)
|
Added |
|
XRFdc_SetFabRdVldWordsObs (Gen 3/DFE)
|
Added |
|
XRFdc_GetFabRdVldWordsObs (Gen 3/DFE)
|
Added |
|
XRFdc_SetupFIFOObs (Gen 3/DFE)
|
Added |
|
XRFdc_SetupFIFOBoth (Gen 3/DFE)
|
Added |
|
XRFdc_GetFIFOStatusObs (Gen 3/DFE)
|
Added |
|
XRFdc_ResetInternalFIFOWidth (Gen 3/DFE)
|
Added |
|
XRFdc_ResetInternalFIFOWidthObs (Gen 3/DFE)
|
Added |
|
XRFdc_SetPwrMode (Gen 3/DFE)
|
Added |
|
XRFdc_GetPwrMode (Gen 3/DFE)
|
Added |
| 06/03/2020 Version
2.3 |
|
AXI4-Stream Related Ports for RF-DACs
|
sXY_axis_tvalid description updated |
|
AXI4-Stream Related Ports for RF-ADCs
|
mXY_axis_tready description updated |
|
Real-Time Signal Interface Ports for Quad RF-ADCs
|
adcXY_clear_or added |
|
Real-Time Signal Interface Ports for Dual RF-ADCs
|
adcXY_ZZ_clear_or added |
|
NCO Frequency Conversion
|
New topic |
|
NCO Setting Example
|
Text/graphic updated |
|
Transmit Transfer Function
|
Text updated |
|
Interface Data Formats
|
Text updated |
|
Dynamic Update Events
|
Table updated |
|
NCO Frequency Hopping
|
Text/tables updated |
|
Multi-Tile Mode
|
Timing diagram and text updated |
|
VOP Update (Gen 3/DFE)
|
New topic |
|
RF-ADC Data Capture Block
|
0x0000_000C Tile Enable added |
|
RF-DAC Data Stimulus Block
|
0x0000_000C Tile Enable added |
|
struct XRFdc_Threshold_Settings
|
Note added |
|
XRFdc_ThresholdStickyClear
|
Note added |
|
Over Voltage (Gen 3/DFE)
|
Graphic added |
|
Real-Time DSA Signal Interface for Quad RF-ADCs (Gen 3/DFE)
|
New topic |
|
Real-Time VOP Signal Interface Ports for RF-DACs (Gen 3/DFE)
|
New topic |
|
Real-Time DSA Signal Interface for Dual RF-ADCs (Gen 3/DFE)
|
New topic |
|
DSA Operation Details (Gen 3/DFE)
|
Text updated |
|
Over Voltage (Gen 3/DFE)
|
Graphic added |
|
VOP Details (Gen 3/DFE)
|
Topic updated |
|
Decimation Filter Details (Gen 3/DFE)
Inverse Sinc Filter for Mix-Mode (Gen 3/DFE)
Interpolation Filter Details (Gen 3/DFE)
Image Rejection Filter Details (Gen 3/DFE)
|
N(bit) added |
|
RF-DAC Numerical Controlled Oscillator and Mixer
|
Note added |
|
RF-DAC Datapath Mode (Gen 3/DFE)
|
Table note added |
| Clock Forwarding from RF-DAC to RF-ADC ( Gen 3) |
Graphic updated |
|
XRFdc_SetDataPathMode (Gen 3/DFE)
|
Table updated |
| 10/30/2019 Version
2.2 |
| All |
Terminology updated to Quad and Dual converter types |
|
Background Calibration Process
|
Signal name update |
|
PLL Parameters
|
New topic |
|
Detailed Description
|
Updated |
|
NCO Frequency Hopping
|
Updated |
|
Multi-Tile Mode
|
Updated |
|
User Parameters
|
Updated |
|
Test Bench
|
Updated |
|
Analog Signaling
|
Updated |
|
struct XRFdc_Mixer_Settings
|
Valid macros for MixerType updated |
|
User API Functions
Interrupt Handling
|
New |
|
struct XRFdc
|
Updated driver title |
| 05/22/2019 Version
2.1 |
|
NCO Frequency Hopping
|
Updated content |
|
Over Voltage (Gen 1/Gen 2)
|
Updated content |
|
Interrupt Handling
|
Interrupt handling updated |
|
System Clocking Tab
|
New tab in AMD Vivado™
IDE |
|
Clocking
|
Updated content |
|
Address Space
|
Address space updated |
|
Hardware Trigger
|
New topic |
|
Overview
|
Updated driver files list |
| Summary Tab |
Removed tab in Vivado
IDE |
|
struct XRFdc_Calibration_Coefficients
struct XRFdc_Cal_Freeze_Settings
XRFdc_DisableCoefficientsOverride
XRFdc_SetCalCoefficients
XRFdc_GetCalCoefficients
XRFdc_SetCalFreeze
XRFdc_GetCalFreeze
XRFdc_SetDither
XRFdc_GetDither
XRFdc_GetPLLConfig
XRFdc_GetMaxSampleRate
XRFdc_GetMinSampleRate
|
New driver topics |
|
XRFdc_IsHighSpeedADC
|
Replaces XRFdc_IsADC4GSPS |
|
XRFdc_SetInvSincFIR
XRFdc_GetInvSincFIR
XRFdc_IntrEnable
XRFdc_IntrDisable
XRFdc_IntrClr
XRFdc_GetIntrStatus
XRFdc_IntrHandler
|
Updated driver information |
| 12/05/2018 Version
2.1 |
|
RF Analyzer
|
Added RF Analyzer appendix. |
|
Reset Count Register (0x0038)
|
Added register. |
|
Over Voltage (Gen 1/Gen 2)
|
Updated section. |
|
PLL
|
Updated section. |
| Summary Tab |
New tab documented. |
|
Example Design
|
Example Design chapter updated. |
|
Test Bench
|
Test Bench chapter updated. |
|
User API Functions
|
Added to and updated section. |
| In-line Functions |
Added in-line functions. |
| 04/17/2018 Version
2.0 |
|
Data Structures
User API Functions
In-line Functions
|
Added and updated driver commands. |
| 04/04/2018 Version
2.0 |
|
Port Descriptions
|
Added clarification to the notes in the Port Description
tables. |
|
Multi-Tile Synchronization Ports
|
Added Multi Converter Synchronization Ports table. |
|
Calibration Freeze Ports for Quad RF-ADC Tiles
Calibration Freeze Ports for Dual RF-ADC Tiles
|
Added Calibration Freeze Ports tables. |
|
Basic Tab
Advanced Tab
|
Added Basic and Advanced Vivado IDE tab descriptions. |
|
RF-ADC Tab
RF-DAC Tab
|
Improved description of RF-ADC and RF-DAC
Vivado IDE tabs. |
|
Example Design
|
Added information on IP Integrator example design. |
|
RF-DAC Data Stimulus Block
|
Added information on RF-DAC source register map. |
| 10/04/2017 Version
1.1 |
| Major content addition and IP core updates. |
Major content addition and IP core updates. |
| 04/05/2017 Version
1.0 |
|
Initial release.
|
N/A |