VOP Update (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The real-time VOP signal interface enables the RF-DAC output power to be adjusted from the PL. The process for updating the output power is shown below.

Figure 1. VOP Update

When the dacX_vop_busy output for the tile is Low the update input can be asserted together with the desired VOP code. The VOP code is a 10-bit value indicating the desired full scale current setting. Multiple slices in the same tile can be updated simultaneously by asserting their update inputs at the same time. The VOP code should be held on the dacXY_vop_code input until the process has completed. The busy signal is asserted during the update process and during tile start up.

The done output (dacXY_vop_done) is asserted when the VOP update has completed successfully. The maximum jump allowed between two VOP updates is approximately ±10% of the current VOP value in mA. If a larger jump is requested, the registers in the converter will not be written and the done signal will not be asserted. The API can be used to set the correct VOP value if a larger jump is required.

When more than one RF-DAC channel is modified at the same time the dacXY_vop_done signal for each channel is asserted when the VOP update for that channel has completed. The dacX_vop_busy signal remains high until all channels have been updated. An example where channels 0 and 1 in converter 0 are updated simultaneously is shown below.

Figure 2. Multiple VOP Updates Example

Note: The RFdc driver can also be used to update the variable output power. However, the driver and real-time signal methods are mutually exclusive. The driver should not be used to modify the output power when the VOP signal interface is being used.