Time Skew Calibration Block (TSCB) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

This block corrects for the time skews among the interleaving sub-RF-ADCs. Any residual difference can result in spurious signal at +/-fin + (k/N)*Fs, where Fs is the sample rate of the RF-ADC, N is the number of sub-RF-ADCs, fin is the frequency of the input signal. The TSCB requires the presence of an input signal. The minimum power of this input signal is -40 dBFS. This block should be in the freeze mode whenever the input signal power drops below -40 dBFS for longer than 100 μs.