Tile <n> Registers - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

Do not attempt to write to any tile specific registers while the power-on state machine is operating. To ensure the power-on state machine is not running prior to any register access, poll the Restart Power-On State Machine register (for tile <n>) and wait for it to read all zeros.

Table 1. Tile <n> Registers
ADDR[12:0] Function
0x0000 Reserved
0x0004 Restart Power-On State Machine Register
0x0008 Restart State Register
0x000C Current State Register
0x0010 - 0x0034 Reserved
0x0038 Reset Count Register
0x003C - 0x0080 1 Reserved
0x0084 1 Clock detector status (Gen 3/DFE)
0x0088 - 0x00FC 1 Reserved
0x003C - 0x00FC Reserved
0x0100 Post-Implementation Simulation Speedup Register
0x0104 - 0x01FC Reserved
0x0200 Interrupt Status Register
0x0204 Interrupt Enable Register
0x0208 Converter 0 Interrupt Register
0x020C Converter 0 Interrupt Enable Register
0x0210 Converter 1 Interrupt Register
0x0214 Converter 1 Interrupt Enable Register
0x0218 Converter 2 Interrupt Register 2
0x021C Converter 2 Interrupt Enable Register 2
0x0220 Converter 3 Interrupt Register 2
0x0224 Converter 3 Interrupt Enable Register 2
0x0228 RF-DAC/RF-ADC Tile <n> Common Status Register
0x022C Reserved
0x0230 RF-DAC/RF-ADC Tile <n> Disable Register
0x0234-0x3FFF Reserved
  1. Addresses 0x003C to 0x00FC are Reserved in Gen 1/Gen 2 devices.
  2. In the RFdc driver API, for a dual RF-ADC tile, Block_Id 0 refers to converters 0 and 1, and Block_Id 1 refers to converters 2 and 3.