Figure 1. Quad RF-ADC
Real Input to Real Output
Figure 2. Quad RF-ADC Real Input to Real Output
IP Core Configuration
The following figure shows a Quad RF-ADC real data input to real data output, 1x decimation, the mixer bypassed, and running at a 500 MHz AXI4-Stream clock.
Figure 3. Quad RF-ADC
Real Input to Real Output Timing
