Hysteresis Counter - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

The hysteresis counter block following the leaky filter, consists of a threshold comparator and two counters, all of them are user programmable. The hysteresis counter is used to further filter the signal magnitude from the leaky integrator, to avoid oscillation when the signal amplitude is close to the threshold level, and outputs a stable state, the ON or OFF.

The signal is deemed to be ON if the signal is greater or equal than the threshold value for 2 * "high counter" number of consecutive cycles. In a similar manner the signal is considered to be OFF if the signal is less than the "threshold" for 2 * "low counter" number of consecutive cycles. The low and high counters are immediately synchronously reset if the previous condition is not met. The "ON" or "OFF" output will keep its state until changed by another counter.

The threshold level is 15 bits unsigned value, the following formula converts the threshold level to full scale logarithmic value:

  • Threshold (dBFS) = 20 * Log10(Threshold (15 bits unsigned)/215)

Both the high counter and low counter are 17 bits unsigned value, while the high 16-bits are user programmable, the least significant bit is always 0.