RF-ADC Interface Data and Clock Rates - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The total data rate per channel to the PL is determined by a number of factors, RF-ADC sample rate, decimation factor, and I/Q/Real data formats. The gearbox FIFOs provide a way of interfacing this data rate to the clock frequency of the PL design, by allowing the number of words per clock to be altered. The only requirements are that the number of words and clock rate combine to match the output data rate of the RF-ADC and the decimation rate, if enabled. All RF-ADCs in a tile share a common interface clock frequency. This is shown by the following equations, where 2GIQMode is set to 2 for a Quad RF-ADC tile and I/Q mode is enabled and set to 1 otherwise.

PLDataRate = (ADCDataRate x 2GIQMode) / DecimationRate

AXI4-Stream Clock x PLNumWords = PLDataRate

AXI4-Stream Clock = PLDataRate / PLNumWords

The core automatically calculates the data rates based on the RF-ADC sample rate and datapath settings. This is shown in the following figure. See the RF-ADC Converter Configuration for information on the settings.

Figure 1. RF-ADC Interface Data and Clock Rates Configuration

Because each tile has independent clocking, sample rates, clock rates, PL rates, and configurations can be specified on a per-tile basis.