The following table shows key parameters of the on-chip PLL.
| Reference Divider (R) | Feedback Divider (N) | Output Divider (M) | VCO Frequency (GHz) |
|---|---|---|---|
| 1 to 4 | 13 to 160 | 2, 3, 4 ,6, 8,… (even numbers ≤ 64) | 8.5 to 13.2 |
| Reference Divider (R) | Feedback Divider (N) | Output Divider (M) | VCO Frequency (GHz) |
|---|---|---|---|
| 1 to 4 | 13 to 160 | 1, 2, 3, 4, 6, 8,… (even numbers ≤ 64) | 7.863 to 13.76 |
CAUTION:
For Gen 3/DFE, the on-chip PLL covers all possible sampling frequencies for
RF-ADC, while for the RF-DAC, there is a "hole" which on-chip PLL does not support. The IP will
force you to avoid this "hole" in the frequency range.