PLL Parameters - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

The following table shows key parameters of the on-chip PLL.

Table 1. PLL Parameters (RF-ADC Gen 1/Gen 2/Gen 3/DFE and RF-DAC Gen 1/Gen 2)
Reference Divider (R) Feedback Divider (N) Output Divider (M) VCO Frequency (GHz)
1 to 4 13 to 160 2, 3, 4 ,6, 8,… (even numbers ≤ 64) 8.5 to 13.2
Table 2. PLL Parameters for the RF-DAC (Gen 3/DFE)
Reference Divider (R) Feedback Divider (N) Output Divider (M) VCO Frequency (GHz)
1 to 4 13 to 160 1, 2, 3, 4, 6, 8,… (even numbers ≤ 64) 7.863 to 13.76
CAUTION:
For Gen 3/DFE, the on-chip PLL covers all possible sampling frequencies for RF-ADC, while for the RF-DAC, there is a "hole" which on-chip PLL does not support. The IP will force you to avoid this "hole" in the frequency range.