Master Reset Register (0x0004) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English
Table 1. Master Reset Register (0x0004)
Bit Default Value Access Type Description
31:1 - - Reserved
0 0 R/W Auto Clear

Reset All Tiles. Write 1 to this bit to reset all logic in the core and restart the power-on sequence of all converters in the core.

Each converter is configured as per the settings chosen during core generation. The AXI4-Lite registers are unaffected by this reset with the exception of bits 15:8 in the Restart State Register for each tile which is set to 0 automatically. The end state (bits 7:0) is not affected by this reset so the power-up sequence for each tile starts from state 0 and runs to the value programmed in bits 7:0 of the Restart State register for each tile (the default end state is 0x0F).