Real-Time Signal Interface Ports for Quad RF-ADCs - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English
Table 1. Real-Time Signal Interface Ports for Quad RF-ADCs
Port Name 1, 2 I/O Clock Description
adcXY_pl_event In clk_adcX RF-ADC PL event

Assert to update RF-ADC settings from the PL.

adcXZ_over_range Out Async Over range output. A High on this output indicates that the signal exceeds the full-scale input of the RF-ADC.
adcXZ_over_threshold1 Out clk_adcX Over threshold1 output

Signal amplitude level is above programmable threshold 1.

adcXZ_over_threshold2 Out clk_adcX Over threshold2 output

Signal amplitude level is above programmable threshold 2.

adcXZ_over_voltage Out Async Over voltage output

An Over Voltage condition occurs when a signal far exceeds the normal operating input-range.

adcXZ_clear_or In s_axi_aclk When asserted the over range is cleared.
adcXY_datapath_overflow Out Async RF-ADC datapath overflow

Asserted when a sub-block in the signal chain has detected that the output signal amplitude has exceeded full scale and has been saturated.

adcXZ_clear_ov 3 In s_axi_aclk When asserted the over voltage output is cleared.
adcXZ_cm_over_voltage 3 Out Async Common mode over voltage output. A High on this output indicates that the input signal common mode exceeds safe operating conditions.
adcXZ_cm_under_voltage 3 Out Async Common mode under voltage. A High on this output indicates that the input signal common mode is too low for safe operation.
adcX_sysref_gate 3 In s_axi_aclk When asserted the sysref is not acted on by the RF-ADC.
adcX_sync_out 3 Out clk_adcX This is a one cycle wide pulse that asserts when a sysref event has arrived and indicates the divider values are valid.
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3). Z refers to the location of the RF-ADC in the tile (0 to 3).
  2. See RF-ADC Threshold and Over Range Settings for details on the real-time signals.
  3. Gen 3/DFE only.