| Port Name | I/O | Clock | Description |
|---|---|---|---|
| s_axi_aclk | In | N/A | AXI clock input (continuous clock) |
| s_axi_aresetn | In | N/A | Active-Low reset for the aclk domain. The deassertion of the reset
should be synchronous to s_axi_aclk. The reset triggers a restart of the power-on state machine. See Power-up Sequence for details. |
| s_axi_awaddr[17:0] | In | s_axi_aclk | Write Address |
| s_axi_awvalid | In | s_axi_aclk | Write Address Valid |
| s_axi_awready | Out | s_axi_aclk | Write Address Ready |
| s_axi_wdata[31:0] | In | s_axi_aclk | Write Data |
| s_axi_wstrb[3:0] | In | s_axi_aclk | Write Data Byte Strobe |
| s_axi_wvalid | In | s_axi_aclk | Write Data Valid |
| s_axi_wready | Out | s_axi_aclk | Write Data Ready |
| s_axi_bresp[1:0] | Out | s_axi_aclk | Write Response |
| s_axi_bvalid | Out | s_axi_aclk | Write Response Valid |
| s_axi_bready | In | s_axi_aclk | Write Response Ready |
| s_axi_araddr[17:0] | In | s_axi_aclk | Read Address |
| s_axi_arvalid | In | s_axi_aclk | Read Address Valid |
| s_axi_arready | Out | s_axi_aclk | Read Address Ready |
| s_axi_rdata[31:0] | Out | s_axi_aclk | Read Data |
| s_axi_rresp[1:0] | Out | s_axi_aclk | Read Response |
| s_axi_rvalid | Out | s_axi_aclk | Read Data Valid |
| s_axi_rready | In | s_axi_aclk | Read Data Ready |
| irq | Out | s_axi_aclk | Interrupt output |