RF Analyzer - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

The RF Analyzer provides a method of evaluating and monitoring the converters in hardware. An overview of the system is given below. The IP example design blocks are outlined in yellow.

Figure 1. RF Analyzer

The RF Analyzer GUI provides access to the data stimulus and capture blocks together with data analysis tools for processing the data. The MicroBlaze™ provides system configuration and control.

The major changes to the existing example design are:

  • The addition of a MicroBlaze to facilitate the configuration and control of the IP subsystem.
  • The inclusion of a JTAG to AXI IP core to enable communication between the RF Analyzer GUI and the IP subsystem.
  • Clocking logic to generate the AXI4-Stream clocks from the converter output clocks.
  • Clocking logic to generate the AXI4-Lite clock from the FPGA startup component.

A block diagram of the expanded example design is shown below.

Figure 2. RF Analyzer Example Design

The base IP integrator example design is as described in the Example Design Chapter. The extended IP integrator example design includes the MicroBlaze™ , JTAG to AXI, and clocking blocks to support the RF Analyzer.