Product Specification - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The Zynq™ UltraScale+™ RFSoC RF Data Converter IP core provides a way of instantiating all the RF-DAC and RF-ADC blocks in Zynq UltraScale+ RFSoCs in IP integrator. A single IP core instance allows access to all converters in the device. The IP ensures that all enabled blocks are powered up and that unused converters are disabled.

Figure 1. IP Core Overview (Gen 1/Gen 2)
Figure 2. IP Core Overview (Gen 3/DFE)

An RF-ADC tile has two or four RF-ADCs; for Gen 1/Gen 2 devices an RF-DAC tile has four RF-DACs; for Gen 3/DFE devices an RF-DAC tile can have two or four RF-DACs. The number of converters and the maximum sample rate depend on the device and package. The converters in each tile are the same type.