| Bit | Default Value | Access Type | Description 1,2 |
|---|---|---|---|
| 31:4 | - | RO | Reserved |
| 3 | PLL locked. Asserted when the tile PLL has achieved lock. | ||
| 2 | Power-up state. Asserted when the tile is in operation. | ||
| 1 | Supplies up. Asserted when the external supplies to the tile are stable. | ||
| 0 | Clock present. Asserted when the reference clock for the tile is present. | ||
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