RF-DAC/RF-ADC Tile <n> Common Status Register (0x0228) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English
Table 1. RF-DAC/RF-ADC Tile <n> Common Status Register (0x0228)
Bit Default Value Access Type Description 1,2
31:4 - RO Reserved
3 PLL locked. Asserted when the tile PLL has achieved lock.
2 Power-up state. Asserted when the tile is in operation.
1 Supplies up. Asserted when the external supplies to the tile are stable.
0 Clock present. Asserted when the reference clock for the tile is present.
  1. <n> is 0 to 3.
  2. See Register Space for register <n> address.