Synchronization Steps - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

At a high-level, the synchronization steps that are carried out are as follows:

  1. Enable all clocks and SYSREF generators

    Both analog and digital clocks must be running and locked before synchronization begins. Any change to the clocks requires resynchronization.

  2. SYSREF analog capture

    Ensures SYSREF is safely captured by auto-adjusting the internal SYSREF programmable delay for setup/hold. This is done for each tile and requires a number of periodic SYSREF pulses so that the optimal delay value can be determined. As a result, a periodic SYSREF clock is needed for the MTS process.

  3. Clock divider reset

    When all tiles are safely capturing SYSREF, a subsequent SYSREF edge is used to synchronize all divider phases.

  4. FIFO latency measure and adjust

    Analog SYSREF and PL_Sysref signals are used to measure the latency through each FIFO. Use the measurements across all tiles to adjust the latencies so that they match.

  5. Synchronize digital features with SYSREF dynamic update events

    When digital features which will impact the tile alignment are enabled, the related digital function blocks must be initialized/updated with SYSREF dynamic update event. These digital features include fine mixer/NCO, QMC, and coarse delay.

Steps 2, 3, and 4 are handled automatically by the IP core and RFdc driver API.

When the API is used to modify digital settings that impact the FIFO clock rate or width, the synchronization process must be restarted. The synchronization process must also be restarted after any tile involved in the MTS process is powered down or restarted.