Over Amplitude (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

When an Over-Amplitude occurs the on-chip DSA is automatically set. During this time the input buffer remains active and the attenuated data is sent to the digital circuitry, and the 'sticky' over_voltage output signal is asserted and remains asserted until you clear it.

To clear the over_voltage signal assert the clear_ov signal, which is high active input, and, when asserted, returns the DSA setting to the previously programmed user value.

Figure 1. Amplitude Over-Voltage Assertion and Clearing

The previous figure shows the amplitude over-voltage being set in the presence of a large signal. The output signal over_voltage is asserted, and remains set (sticky) until you clear it, while the signal into the RF-ADC is attenuated automatically (Auto). It also shows what happens if you clear the event while the large signal persists - it causes the over_voltage signal to reassert and the attenuation continues to be set automatically. To avoid the over_voltage signal reassertion while a large signal persists, you should set the DSA to a high value before asserting clear_ov signal, or make sure the input large signal has been attenuated by external devices.

For the attenuation and input voltage specifications see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).