struct XRFdc_Tile_Clock_Settings (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

This structure is used to set or get the internal tile clock settings. It is information only; you do not need to set it.

u8 SourceType;
u8 SourceTile;
u8 PLLEnable;
double RefClkFreq;
double SampleRate;
u8 DivisionFactor;
u8 Delay;
u8 DistributedClock;


u32 SourceType
The source tile type. RF-ADC or RF-DAC; 0 for RF-ADC and 1 for RF-DAC.
u32 SourceTile
RF-ADC/RF-DAC tile number of the source tile. Valid values are 0-3.
u8 PLLEnable
Enable internal PLL.
double RefClkFreq
The input reference clock to the tile.
double SampleRate
The sampling rate of the tile.
u8 DivisionFactor
The clock divider if bypassing PLL.
u8 Delay
Delay the delay of the source clock to the tile.
u8 DistributedClock
The options to distribute this tile's clock. Valid values are 0 (none), 1 (the received reverence clock), and 2 (a full rate clock from the internal divider).
Table 1. Valid Macros for DistributedClock
Macro Description
XRFDC_DIST_OUT_NONE Do not distribute the clock of this tile
XRFDC_DIST_OUT_RX Distribute this RX clock of this tile
XRFDC_DIST_OUT_OUTDIV Distribute the clock out of the output divider of this tile