The sampling clock generated by on-chip PLL is forwarded from the RF-DAC group to RF-ADC Tile 3 and/or 2, Tile 3 and 2 have built-in clock dividers of 1 or 2 to output desired clock frequencies, note the clock divider in Tile 3 and 2 are only available for quad RF-ADC tiles in this case. The RF-ADC Tile 0 and 1 share clocks generated by the on-chip PLL.
Figure 1. On-chip PLL Clock Forwarding to RF-ADC (Gen 3)
Figure 2. On-chip PLL Clock Forwarding to RF-ADC (DFE)