Power-up Sequence - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

Tiles consist of different independent blocks, powered from different power supplies and clocked by different versions of the main clock. Tiles must be brought up in a known sequence for the converters to function correctly. The power-up state machine is run automatically when the device is configured or reconfigured with a bitstream but it can also be rerun at any time under software control.

Important: The IP should only be started when all external clocks are running and stable (glitch-free). The IP AXI4-Lite reset (s_axi_aresetn) can be held Low if the startup needs to be delayed until the external clocks are valid.
Figure 1. POR Finite State Machine