The AMD Zynq™
UltraScale+™ RFSoC has a very
flexible clocking and data interface to enable a multitude of different applications
within the same device. Each RF-ADC/RF-DAC tile has its own independent clocking and data
infrastructure, which allows each tile to be driven with individual sample rates, and PL
data-word widths. The converters within a single tile share the clocking and data
infrastructure, so the sample rates and latency are fixed. However, certain applications
might require more than one tile, or even more than one Zynq UltraScale+ RFSoC to be used together. For these applications,
matching converter latency across tiles is critical. The multi-tile synchronization
(MTS) feature can be used to achieve relative and deterministic multi-tile and
multi-device alignment.
Note: In
this documentation multi-tile synchronization (MTS) is synonymous with
multi-converter synchronization.