Clock Ports Common to RF-DAC Tile

Clock Ports Common to RF-DAC Tile - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID

PG269

Release Date

2024-05-30

Version

2.6 English

Table 1. Clock Ports Common to RF-DAC Tile
Port Name¹	I/O	Clock	Description
dacX_clk_p	In	N/A	RF-DAC on-chip PLL reference clock or sampling clock input
dacX_clk_n	In	N/A	RF-DAC on-chip PLL reference clock or sampling clock input
clk_dacX	Out	N/A	Output clock to user logic
X refers to the location of the tile in the converter column.