Figure 1. Quad RF-ADC Real Input to I/Q
Output
Figure 2. Quad RF-ADC Real Input to I/Q
Output IP Core Configuration
The following figure shows a Quad RF-ADC real input data to I/Q output data, 1x decimation, the mixer enabled, and running at a 500 MHz AXI4-Stream clock. Note that each I/Q channel is interleaved on the output data stream.
Figure 3. Quad RF-ADC Real Input to I/Q
Output Timing
