On-chip Clock Distribution (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

The Zynq UltraScale+ RFSoC contains multiple RF-ADC and RF-DAC tiles. Each tile runs independently at its own tile clock (T1). The T1 clock can be an external clock, from the on-chip PLL, or from a distributed sampling clock.

An on-chip clock distribution network allows one tile to forward its clock to adjacent tiles within the converter tile groups. A tile group is an adjacent set of tiles; multiple groups are possible depending on application requirements until they are built from successive tiles in the device tile sequence. A tile group can comprise of RF-DAC tiles, RF-ADC tiles, or both of them. The tile group imposes the following constraints on the design:

  • Each tile group can only have one source tile.
  • Each tile in a tile group which is not the source tile must use the forwarded clock; skipping over a tile using a different clock is not allowed.
  • When a tile group comprise of both RF-DAC tiles and RF-ADC tiles, the source tile must be a RF-DAC tile; forwarding clock from RF-ADC tile to RF-DAC tile is not allowed.

The forwarded clock signal from the source tile can be:

  1. External sampling clock
  2. External reference clock used with internal PLLs
  3. Sampling clock generated by on-chip PLL
CAUTION:
Some tiles in specific packages do not have external clock input pins. These tiles can only accept forwarded clocks.