struct XRFdc_PLL_Settings - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

This structure is for internal driver use.

u32 Enabled;          
double RefClkFreq;
double SampleRate;
u32 RefClkDivider;
u32 FeedbackDivider;
u32 OutputDivider;
u32 FractionalMode;   
u64 FractionalData; 
u32 FractWidth;


u32 Enabled
Indicates if the PLL is enabled (1) or disabled (0).
double RefClkFreq
Reference clock frequency (MHz).
double SampleRate
Sampling rate (GHz).
u32 RefClkDivider
Reference clock divider.
u32 FeedbackDivider
Feedback divider.
u32 OutputDivider
Output divider.
u32 FractionalMode
Fractional mode. Currently not supported.
u64 FractionalData
Fractional part of the feedback divider. Currently not supported.
u32 FractWidth
Fractional data width. Currently not supported.