Dual and Quad RF-ADC/RF-DAC Tiles - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)
Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

There are two types of converter tiles for the RF-ADCs, called Dual and Quad tiles. For RF-ADCs, the converters in the Dual tiles have different maximum sampling rates and different interleaving factors to the Quad tiles. Gen 1/Gen 3/DFE devices have both type of tiles, while Gen 2 devices consist of Quad RF-ADC tiles only.

Quad RF-DAC tiles are available in Gen 1/Gen 2 devices and Dual RF-DAC tiles are additionally available in Gen 3/DFE devices; the Dual RF-DAC tiles have two dedicated DUCs for each channel to support dual-band applications. There is no performance difference between converters in both types of RF-DAC tile.

Note: In this document, colored table rows call attention to specific Gen 3/DFE device information.
Table 1. Tile Configuration
Tile Type Number of Converters Device Type Notes
Quad RF-ADC 4 Gen 1/Gen 2/Gen 3/DFE Each RF-ADC has an interleaving factor of four.
Dual RF-ADC 2 Gen 1/Gen 3/DFE Each RF-ADC has an interleaving factor of eight, hence double the sampling rate of the converters in the Quad RF-ADC tiles.
Quad RF-DAC 4 Gen 1/Gen 2/Gen 3/DFE Each RF-DAC has one dedicated DUC.
Dual RF-DAC 2 Gen 3/DFE Each RF-DAC has two dedicated DUCs. For Gen 3/DFE devices featuring Quad RF-DACs or a combination of Quad and Dual RF-DACs, all tiles have external clock inputs.
  1. Gen 3/DFE devices with one RF-ADC per tile are considered as Dual RF-ADCs with the upper ADC (input VinX_23) unavailable. All data paths are available for use on these devices. These devices do not support I/Q input signals.
  2. Gen 3/DFE devices with one RF-DAC per tile are considered as Dual RF-DACs with the upper DAC (output VoutX2) unavailable. All data paths are available for use on these devices. These devices do not support I/Q output signals.

See the Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) for an overview of the maximum sampling rates and the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) for the exact specifications.

The following figures illustrate the tile structures. Dashed lines indicate multiple bands cases.

Figure 1. RF-ADC Tile Structure
Note: Dual RF-ADC tile applies to Gen 1/3/DFE.
Figure 2. RF-DAC Tile Structure
Note: Dual RF-DAC tile applies to Gen 3/DFE.
Figure 3. Single Converter Tile Structure (Gen 3)
Note: Single RF-DAC and RF-ADC tiles apply to Gen 3.