Power-Down Tile - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

To power down a tile, the power-on sequence is rerun in the same way as restarting a tile but with the End State set to 3 rather than F. Setting the End State to 3 makes the power-on sequencer clear all the registers without performing a full power-on sequence. Perform the following steps to power down a tile:

  1. Write 0x0000_0003 to the individual tile Restart State register. When using multi-tile synchronization in Gen 3/DFE devices, if the tile is in the SYSREF chain, 0x0000_0006 should be written to the individual tile Restart State register.
  2. Write 0x0000_0001 to the tile<n> Restart Power-On State Machine register to restart the tile.
  3. Poll the tile<n> Restart Power-On State Machine register to check operation is complete; the power-down sequence is complete when this register reads all zeros.