Real-Time DSA Signal Interface for Dual RF-ADCs (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
Release Date
2.6 English
Table 1. Real Time DSA Signal Interface Ports for Dual RF-ADCs
Port Name 1 I/O Clock Description
adcX_ZZ_dsa_code[4:0] In s_axi_aclk RF-ADC attenuation code
adcX_dsa_update In s_axi_aclk Asserted to latch the attenuation codes into the RF-ADC
  1. X refers to the location of the tile in the converter column. ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).