AXI4-Stream Observation Channel Ports for RF-ADCs (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English
Table 1. AXI4-Stream Observation Channel Ports
Port Name 1 I/O Clock Description
mX_axis_obs_aclk In N/A Clock input for RF-ADC observation channel data output
mX_axis_obs_aresetn In N/A Active-Low synchronous reset for the mX_axis_obs_aclk domain. This should be held Low until mX_axis_obs_aclk is stable. The reset can be asserted asynchronously but deassertion must be synchronous to mX_axis_obs_aclk.
mXY_axis_obs_tdata[M:0] 2 Out mX_axis_obs_aclk AXI4-Stream observation channel data output
mXY_axis_obs_tvalid Out mX_axis_obs_aclk AXI4-Stream observation channel valid
mXY_axis_obs_tready In mX_axis_obs_aclk AXI4-Stream channel ready. Not used in IP core.
adcXY_tdd_obs In s_axi_aclk Enable observation channel.
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DDC block in the tile (0 to 3).
  2. M is the number of samples per AXI4-Stream word *16 for converter XY.