RF-DAC Data Stimulus Block - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

The RF-DAC data stimulus block consists of a 128 kbits block RAM that can be loaded with samples which are then sent to the RF-DAC (s) in the Zynq UltraScale+ RF Data Converter core.

Each channel in the stimulus block drives an AXI4-Stream on the Zynq UltraScale+ RF Data Converter IP core. As each converter can have up to four AXI4-Stream interfaces, there are a maximum of 16 channels in the data stimulus block. Each enabled AXI4-Stream interface is mapped into consecutive channels starting with DAC0.

The address map for the data stimulus block is shown below.

Table 1. RF-DAC Data Stimulus Address Map
Address 1 Register Access Type Description
0x0000_0000 Memory ID code RO Memory Information
  • Bit 31. Low. Signaling a data stimulus block.
  • Bits 30:24. Number of channels in the data stimulus block.
  • Bits 23:0. Total memory size of the data stimulus block.
0x0000_0004 Start data R/W Starts the transmission of data
  • Bits 31:1. Reserved
  • Bit 0. Start data (self clearing). Setting this bit high starts the transmission of the data stored in memory to the RF-DAC. To stop transmission the channel is disabled using the channel enable register.
0x0000_0008 Channel enable R/W Enables each channel.
  • Bits 31:16. Reserved
  • Bits 15:0. Channel enable. Each bit controls one channel (bit n controlling channel n). The channel should be enabled before issuing a start data command. To stop the test the channel should be disabled.
0x0000_000C Tile enable R/W Enables each tile
  • Bits 31:4. Reserved
  • Bits 3:0. Tile enable. Each bit controls one tile (bit n controlling tile n). This register can be used to synchronize the data transmission across a tile. The channels should be enabled while the tile enable is low. When the tile enable is asserted data transmission will be started for all channels in the tile at the same time.
0x0000_0010 - 0x0000_004C Samples to generate R/W The number of samples to transmit before wrapping around to the beginning of the sequence. One address per channel.
0x0000_4000 - 0x0000_7FFC Channel 0 memory R/W Channel 0 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0000_8000 - 0x0000_BFFC Channel 1 memory R/W Channel 1 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0000_C000 - 0x0000_FFFC Channel 2 memory R/W Channel 2 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0001_0000 - 0x0001_3FFC Channel 3 memory R/W Channel 3 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0001_4000 - 0x0001_7FFC Channel 4 memory R/W Channel 4 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0001_8000 - 0x0001_BFFC Channel 5 memory R/W Channel 5 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0001_C000 - 0x0001_FFFC Channel 6 memory R/W Channel 6 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0002_0000 - 0x0002_3FFC Channel 7 memory R/W Channel 7 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0002_4000 - 0x0002_7FFC Channel 8 memory R/W Channel 8 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0002_8000 - 0x0002_BFFC Channel 9 memory R/W Channel 9 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0002_C000 - 0x0002_FFFC Channel 10 memory R/W Channel 10 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0003_0000 - 0x0003_3FFC Channel 11 memory R/W Channel 11 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0003_4000 - 0x0003_7FFC Channel 12 memory R/W Channel 12 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0003_8000 - 0x0003_BFFC Channel 13 memory R/W Channel 13 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0003_C000 - 0x0003_FFFC Channel 14 memory R/W Channel 14 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
0x0004_0000 - 0x0004_3FFC Channel 15 memory R/W Channel 15 data stimulus
  • Bits 31:16. Odd data sample
  • Bits 15:0. Even data sample
  1. When the RF Analyzer is enabled, the memory size of the configuration space and the memory allocated to each channel is doubled. Channel 0 memory is accessed in addresses from 0x0_8000 to 0x0_FFFC, channel 1 memory is held in addresses from 0x1_0000 to 0x1_7FFC. The memory space for subsequent channels is similarly increased.