Hardware Trigger - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

Hardware trigger inputs are available. When enabled, asserting the hardware trigger will start the data transmission or capture. This overrides the writes to the Start Data register.

Table 1. RF-DAC Hardware Trigger Interface
Port Name 1 I/O Clock Description
dacX_hw_trigger In s_axi_aclk Hardware trigger. Assert to enable data transmission.Deassert before starting any subsequent data transmission.
dacX_hw_trigger_en In s_axi_aclk Hardware trigger enable. Assert to enable the hardware trigger
  1. X refers to the location of the tile in the converter column.
Table 2. RF-ADC Hardware Trigger Interface
Port Name 1 I/O    
adcX_hw_trigger In s_axi_aclk Hardware trigger. Assert to enable data capture. The input should be deasserted before any subsequent data capture.
adcX_hw_trigger_en In s_axi_aclk Hardware trigger enable. Assert to enable the hardware trigger
  1. X refers to the location of the tile in the converter column.