The maximum sample rate of RF-DAC is derated in sample rate clock forwarding use cases. This is applied for sample clock forwarding from both external inputs or in-tile PLL. To achieve the full sample clock rate, either distribute reference clock to each tile or do not use the clock distribution feature. For derating specifications, see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).