Figure 1.
RF-DAC
Real Input to Real Output
Figure 2. Dual RF-DAC Real Input to Real Output
IP Configuration
The following figure shows a Dual RF-DAC with real input to real output, 1x interpolation, the mixer bypassed, and running at a 400 MHz AXI4-Stream clock.
Figure 3. Dual RF-DAC Real Input to Real Output
Data Timing (Gen 3/DFE)
