PLL Reference Clock Forwarding (Gen 3/DFE) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

Any tile can be a source tile to forward its low frequency reference clock within a tile group, note the constraints mentioned in the previous section. For example, in a tile group comprising of all RF-DAC and RF-ADC tiles, the source tile must be a RF-DAC tile that has external clock input pins.

Figure 1. PLL Reference Clock Forwarding