Input Stage - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The input stage takes as an input N=4 or N=8 input words at T4/T8 clock rate and output a single sample per T4/T8 cycle. The block operates in one of two modes below:

Averaged mode
An averaged amplitude of all sub-ADCs input is used to detect the signal amplitude.
Random Sampling
A single randomly selected data word (sub ADC) is used to detect the signal magnitude.