Calibration Freeze Ports for Dual RF-ADC Tiles - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)
Document ID
PG269
Release Date
2024-05-30
Version
2.6 English
Table 1. Calibration Freeze Ports for Dual RF-ADC Tiles
Port Name 1 I/O Clock Description
adcX_ZZ_int_cal_freeze In s_axi_aclk Signal from the PL to indicate that IP should freeze the calibration. This is typically asserted when the RF-ADC output is below a certain threshold.
adcX_ZZ_cal_frozen Out s_axi_aclk Asserted when the calibration is frozen.
adcX_ZZ_sig_detect 2 Out Async The signal state output from the signal magnitude detector.
  1. X refers to the location of the tile in the converter column. ZZ is either 01 (the lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
  2. Gen 3/DFE only.