For I/Q input to I/Q output, the RF-ADCs are paired.
Figure 1. Quad RF-ADC I/Q Input to I/Q
Output

Figure 2. Quad RF-ADC I/Q Input to I/Q
Output IP Core Configuration

The following figure shows a Quad RF-ADC I/Q to I/Q, 1x decimation, the mixer enabled, and running at a 500 MHz AXI4-Stream clock.
Figure 3. Quad RF-ADC I/Q Input to I/Q
Output Timing
