Converter 0 Interrupt Register (0x0208) - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

Document ID
PG269
Release Date
2024-05-30
Version
2.6 English
Table 1. Converter 0 Interrupt Register (0x0208)
Bit Default Value Access Type Description
31:16 - - Reserved Enable Read back 0
31:20 1 - - Reserved (read back 0)
19 0 RO Flags a common mode under voltage interrupt in the converter 2, 3, 5
18 0 Flags a common mode over voltage interrupt in the converter 2, 3, 5
17:16 - - Reserved (read back 0)
15 0 RO Flags a FIFO overflow in converter when High 5
14 0 Flags a datapath overflow in converter when High 4, 5
13 0 Flags an overflow on the observation channel FIFO in converter when High 2, 3, 5
12:4 - - Reserved (read back 0)
3 0 RO Flags an Over Range interrupt in converter 2, 5
2 0 RO Clear on Read Flags an Over Voltage interrupt in converter 2
1:0 N/A   Reserved (read back 0)
  1. 31:16 is Reserved (read back 0) for Gen 1/Gen 2 devices.
  2. RF-ADC only.
  3. Gen 3/DFE only.
  4. A datapath overflow indicates one of the following conditions has occurred:
    • Interpolation filter overflow in the RF-DAC
    • Decimation filter overflow in the RF-ADC
    • Overflow in the Quadrature Modulation Correction block
    • Overflow in the RF-DAC Inverse Sinc filter
  5. Registers can be cleared using the XRFdc_IntrClr API function, without the need for a reset of the IP.