Changes from V2.0 to V2.1 - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)
Document ID
PG269
Release Date
2024-05-30
Version
2.6 English

Port Changes

In version 2.1 a new port has been added in the Debug group. The powerup_state output will be asserted when the POR Finite State Machine detects an error in the power-up sequence.

Table 1. Port Changes
Port 1 Direction Upgrade Action
adcX_powerup_state Out Leave open
dacX_powerup_state Out Leave open
  1. X refers to the location of the tile in the converter column

Parameter Changes

The mapping of the decimation and interpolation settings into the C_ADC_Decimation_Mode and C_DAC_Interpolation_Mode IP variables has been changed in version 2.1. The changes are shown below.
Table 2. Decimation and Interpolation Parameter Mode Changes
Parameter 1 Version 2.0 Version 2.1
C_ADC_Decimation_ModeXY
  • 0 = Decimation off
  • 1 = Decimation x1
  • 2 = Decimation x2
  • 3 = Decimation x4
  • 4 = Decimation x8
  • 0 = Decimation off
  • 1 = Decimation x1
  • 2 = Decimation x2
  • 4 = Decimation x4
  • 8 = Decimation x8
C_DAC_Interpolation_ModeXY
  • 0 = Interpolation off
  • 1 = Interpolation x1
  • 2 = Interpolation x2
  • 3 = Interpolation x4
  • 4 = Interpolation x8
  • 0 = Interpolation off
  • 1 = Interpolation x1
  • 2 = Interpolation x2
  • 4 = Interpolation x4
  • 8 = Interpolation x8
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC/DDC block in the tile (0 to 3).
A new option has been added to the C_ADC_Mixer_Type and C_DAC_Mixer_Type parameters, The mixers can now be set to "Off" in addition to the previously defined settings.
Table 3. Mixer Type Parameter Changes
Parameter 1 Version 2.0 Version 2.1
C_ADC_Mixer_TypeXY
  • 0 = Bypassed
  • 1 = Coarse
  • 2 = Fine
  • 0 = Bypassed
  • 1 = Coarse
  • 2 = Fine
  • 3 = Off
C_DAC_Mixer_TypeXY
  • 0 = Bypassed
  • 1 = Coarse
  • 2 = Fine
  • 0 = Bypassed
  • 1 = Coarse
  • 2 = Fine
  • 3 = Off
  1. X refers to the location of the tile in the converter column. Y refers to the location of the DUC/DDC block in the tile (0 to 3).