The RF Analyzer IP integrator design can be integrated into user designs.
Access to the RF-DAC
AXI4-Stream interface is provided through the
following ports.
| Port Name 1 | I/O | Clock | Description |
|---|---|---|---|
| sX_axis_aclk | Out | N/A | AXI4-Stream clock output from the MMCM in the clocking block |
| sXY_0_tdata | In | sX_axis_aclk | AXI4-Stream data input |
| sXY_0_tvalid | In | sX_axis_aclk | AXI4-Stream valid |
| sXY_0_tready | Out | sX_axis_aclk | AXI4-Stream ready |
| user_select_XY_0 | In | sX_axis_aclk | When this input is driven High the RF-DAC is driven from the user interface. When Low the RF-DAC is driven by the data stimulus block in the RF Analyzer. |
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The AXI4-Stream interface is routed out to
the user design through the ports described in the following table.
| Port Name 1 | I/O | Clock | Description |
|---|---|---|---|
| mX_axis_aclk | Out | N/A | AXI4-Stream clock output from the MMCM in the clocking block |
| mXY_0_tdata | Out | mX_axis_aclk | AXI4-Stream data output |
| mXY_0_tvalid | Out | mX_axis_aclk | AXI4-Stream valid |
| mXY_0_tready | In | mX_axis_aclk | AXI4-Stream ready. Tie Low when the user interface is not in use. The RF Analyzer data capture block should be disabled when the user interface is in use. |
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