Analog Signaling - 2.6 English

Zynq UltraScale+ RFSoC RF Data Converter v2.6 Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269)

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2.6 English

The RF-DAC and RF-ADC analog I/O are differential and are driven as shown in the following figure in the test bench.

Figure 1. Test Bench Analog Signaling

The internal RF-DAC and RF-ADC model analog functions using Real Number models. In the Verilog example design these must be passed as 64-bit wires, using force and hierarchical assignments to set and read the values.

In Gen 1 and Gen 2 devices the simulated transfer function uses a full scale voltage swing (VFS) of 1.14V and a common mode voltage (VCM) of 1.25V for the RF-ADC. In Gen 3/DFE devices the simulated transfer function uses the same VFS but with a VCM of 0.7V. For the actual full-sale input voltage range see the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926).

A code excerpt from the demo_tb.v file is shown below. This is generated when you generate the example design. This can be used as a guide to show how to drive and read data into RF-DAC and RF-ADC primitives.

// Force the analog signals.
real adc00_p;
real adc00_n;

always @ (*) begin
   // Map the RF-ADC signals to top level
   adc00_p = $bitstoreal(adc_source.vout_00_p);
   adc00_n = $bitstoreal(adc_source.vout_00_n);
   // Force the RF-ADC analog input force 
DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST.VIN0_P = adc00_p;
DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST.VIN0_N = adc00_n;



real dac00_p;
real dac00_n;

always @ (*) begin
   // Map the RF-DAC signals to the top level
   dac00_p = DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_P;
   dac00_n = DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_N;
   // Force the RF-DAC output onto the RF-DAC sink
   force dac_sink.vin_00_p = $realtobits(dac00_p);
   force dac_sink.vin_00_n = $realtobits(dac00_n);

The code excerpt below shows analog data loopback from the RF-DAC to the RF-ADC on a Gen 1 device. Care must be taken to map the RF-DAC analog data output to within the correct range for the RF-ADC data input.

real dac00_p;
real dac00_n;
always @ (*) begin

   dac00_p = DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_P;
   dac00_n = DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_N;

   // Force the ADC analog input
   force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST.VIN_I01_P = 1.25 + (dac00_p-dac00_n); // ADC VCM = 1.25V
   force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST.VIN_I01_N = 1.25 - (dac00_p-dac00_n); // ADC VCM = 1.25V