Figure 1. Dual RF-ADC Real Input to I/Q
Output
Figure 2. Dual RF-ADC Real Input to I/Q
Output IP Core Configuration
The following figure shows a Dual RF-ADC
with real data input to I/Q data output, 1x decimation, the mixer enabled, and running
at a 500 MHz AXI4-Stream clock.
Figure 3. Dual RF-ADC Real Input to
I/Q Output Data Timing
